pwm.h

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/*
 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _HARDWARE_PWM_H
#define _HARDWARE_PWM_H
 
#include "pico.h"
#include "hardware/structs/pwm.h"
#include "hardware/regs/dreq.h"
#include "hardware/regs/intctrl.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM, Enable/disable assertions in the hardware_pwm module, type=bool, default=0, group=hardware_pwm
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM
#ifdef PARAM_ASSERTIONS_ENABLED_PWM // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM PARAM_ASSERTIONS_ENABLED_PWM
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM 0
#endif
#endif


enum pwm_clkdiv_mode
{
    PWM_DIV_FREE_RUNNING = 0, 
    PWM_DIV_B_HIGH = 1,       
    PWM_DIV_B_RISING = 2,     
    PWM_DIV_B_FALLING = 3     
};
 
enum pwm_chan
{
    PWM_CHAN_A = 0,
    PWM_CHAN_B = 1
};

typedef struct {
    uint32_t csr; 
    uint32_t div; 
    uint32_t top; 
} pwm_config;

#ifndef PWM_DREQ_NUM
static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, "");
static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, "");
#define PWM_DREQ_NUM(slice_num) (DREQ_PWM_WRAP0 + (slice_num))
#endif

#ifndef PWM_GPIO_SLICE_NUM
#define PWM_GPIO_SLICE_NUM(gpio) ({             \
    uint slice_num;                             \
    if ((gpio) < 32) {                          \
        slice_num = ((gpio) >> 1u) & 7u;        \
    } else {                                    \
        slice_num = 8u + (((gpio) >> 1u) & 3u); \
    }                                           \
    slice_num;                                  \
})
#endif
 
// PICO_CONFIG: PICO_PWM_CLKDIV_ROUND_NEAREST, True if floating point PWM clock divisors should be rounded to the nearest possible clock divisor rather than rounding down, type=bool, default=PICO_CLKDIV_ROUND_NEAREST, group=hardware_pwm
#ifndef PICO_PWM_CLKDIV_ROUND_NEAREST
#define PICO_PWM_CLKDIV_ROUND_NEAREST PICO_CLKDIV_ROUND_NEAREST
#endif
 
static inline void check_slice_num_param(__unused uint slice_num) {
    valid_params_if(HARDWARE_PWM, slice_num < NUM_PWM_SLICES);
}

static inline uint pwm_gpio_to_slice_num(uint gpio) {
    valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS);
    return PWM_GPIO_SLICE_NUM(gpio);
}

static inline uint pwm_gpio_to_channel(uint gpio) {
    valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS);
    return gpio & 1u;
}

static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correct) {
    c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS)
        | (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB);
}

static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
    valid_params_if(HARDWARE_PWM, div >= 1.f && div < 256.f);
    const int frac_bit_count = REG_FIELD_WIDTH(PWM_CH0_DIV_FRAC);
#if PICO_PWM_CLKDIV_ROUND_NEAREST
    div += 0.5f / (1 << frac_bit_count); // round to the nearest fraction
#endif
    c->div = (uint32_t)(div * (float)(1u << frac_bit_count));
}

static inline void pwm_config_set_clkdiv_int_frac4(pwm_config *c, uint32_t div_int, uint8_t div_frac4) {
    static_assert(REG_FIELD_WIDTH(PWM_CH0_DIV_INT) == 8, "");
    valid_params_if(HARDWARE_PWM, div_int >= 1 && div_int < 256);
    static_assert(REG_FIELD_WIDTH(PWM_CH0_DIV_FRAC) == 4, "");
    valid_params_if(HARDWARE_PWM, div_frac4 < 16);
    c->div = (((uint)div_int) << PWM_CH0_DIV_INT_LSB) | (((uint)div_frac4) << PWM_CH0_DIV_FRAC_LSB);
}
 
// backwards compatibility
static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t div_int, uint8_t div_frac4) {
    pwm_config_set_clkdiv_int_frac4(c, div_int, div_frac4);
}

static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint32_t div_int) {
    pwm_config_set_clkdiv_int_frac4(c, div_int, 0);
}

static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) {
    valid_params_if(HARDWARE_PWM, mode == PWM_DIV_FREE_RUNNING ||
            mode == PWM_DIV_B_RISING ||
            mode == PWM_DIV_B_HIGH ||
            mode == PWM_DIV_B_FALLING);
    c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS)
        | (((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB);
}

static inline void pwm_config_set_output_polarity(pwm_config *c, bool a, bool b) {
    c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS))
        | ((bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB) | (bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB));
}

static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) {
    c->top = wrap;
}

static inline void pwm_init(uint slice_num, pwm_config *c, bool start) {
    check_slice_num_param(slice_num);
    pwm_hw->slice[slice_num].csr = 0;
 
    pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET;
    pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET;
    pwm_hw->slice[slice_num].top = c->top;
    pwm_hw->slice[slice_num].div = c->div;
    pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB);
}

static inline pwm_config pwm_get_default_config(void) {
    pwm_config c = {0, 0, 0};
    pwm_config_set_phase_correct(&c, false);
    pwm_config_set_clkdiv_int(&c, 1);
    pwm_config_set_clkdiv_mode(&c, PWM_DIV_FREE_RUNNING);
    pwm_config_set_output_polarity(&c, false, false);
    pwm_config_set_wrap(&c, 0xffffu);
    return c;
}

static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) {
    check_slice_num_param(slice_num);
    pwm_hw->slice[slice_num].top = wrap;
}

static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) {
    check_slice_num_param(slice_num);
    hw_write_masked(
        &pwm_hw->slice[slice_num].cc,
        ((uint)level) << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB),
        chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS
    );
}

static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_t level_b) {
    check_slice_num_param(slice_num);
    pwm_hw->slice[slice_num].cc = (((uint)level_b) << PWM_CH0_CC_B_LSB) | (((uint)level_a) << PWM_CH0_CC_A_LSB);
}

static inline void pwm_set_gpio_level(uint gpio, uint16_t level) {
    valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS);
    pwm_set_chan_level(pwm_gpio_to_slice_num(gpio), pwm_gpio_to_channel(gpio), level);
}

static inline uint16_t pwm_get_counter(uint slice_num) {
    check_slice_num_param(slice_num);
    return (uint16_t)(pwm_hw->slice[slice_num].ctr);
}

static inline void pwm_set_counter(uint slice_num, uint16_t c) {
    check_slice_num_param(slice_num);
    pwm_hw->slice[slice_num].ctr = c;
}

static inline void pwm_advance_count(uint slice_num) {
    check_slice_num_param(slice_num);
    hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS);
    while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) {
        tight_loop_contents();
    }
}

static inline void pwm_retard_count(uint slice_num) {
    check_slice_num_param(slice_num);
    hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS);
    while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) {
        tight_loop_contents();
    }
}

static inline void pwm_set_clkdiv_int_frac4(uint slice_num, uint8_t div_int, uint8_t div_frac4) {
    check_slice_num_param(slice_num);
    valid_params_if(HARDWARE_PWM, div_int >= 1);
    static_assert(REG_FIELD_WIDTH(PWM_CH0_DIV_FRAC) == 4, "");
    valid_params_if(HARDWARE_PWM, div_frac4 < 16);
    pwm_hw->slice[slice_num].div = (((uint)div_int) << PWM_CH0_DIV_INT_LSB) | (((uint)div_frac4) << PWM_CH0_DIV_FRAC_LSB);
}
 
// backwards compatibility
static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t div_int, uint8_t div_frac4) {
    pwm_set_clkdiv_int_frac4(slice_num, div_int, div_frac4);
}

static inline void pwm_set_clkdiv(uint slice_num, float divider) {
    check_slice_num_param(slice_num);
    valid_params_if(HARDWARE_PWM, divider >= 1.f && divider < 256.f);
    uint8_t i = (uint8_t)divider;
    uint8_t f = (uint8_t)((divider - i) * (0x01 << 4));
    pwm_set_clkdiv_int_frac4(slice_num, i, f);
}

static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) {
    check_slice_num_param(slice_num);
    hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB | bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB,
                     PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS);
}
 

static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) {
    check_slice_num_param(slice_num);
    valid_params_if(HARDWARE_PWM, mode == PWM_DIV_FREE_RUNNING ||
                         mode == PWM_DIV_B_RISING ||
                         mode == PWM_DIV_B_HIGH ||
                         mode == PWM_DIV_B_FALLING);
    hw_write_masked(&pwm_hw->slice[slice_num].csr, ((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS);
}

static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) {
    check_slice_num_param(slice_num);
    hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS);
}

static inline void pwm_set_enabled(uint slice_num, bool enabled) {
    check_slice_num_param(slice_num);
    hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(enabled) << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS);
}

static inline void pwm_set_mask_enabled(uint32_t mask) {
    pwm_hw->en = mask;
}

#ifndef PWM_DEFAULT_IRQ_NUM
#if PICO_RP2040
#define PWM_DEFAULT_IRQ_NUM() PWM_IRQ_WRAP
#else
#define PWM_DEFAULT_IRQ_NUM() PWM_IRQ_WRAP_0
// backwards compatibility with RP2040
#define PWM_IRQ_WRAP          PWM_IRQ_WRAP_0
#define isr_pwm_wrap          isr_pwm_wrap_0
#endif
#endif

static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) {
    check_slice_num_param(slice_num);
    if (enabled) {
        hw_set_bits(&pwm_hw->inte, 1u << slice_num);
    } else {
        hw_clear_bits(&pwm_hw->inte, 1u << slice_num);
    }
}

static inline void pwm_set_irq0_enabled(uint slice_num, bool enabled) {
    // irq0 always corresponds to the default IRQ
    pwm_set_irq_enabled(slice_num, enabled);
}
 
#if NUM_PWM_IRQS > 1
static inline void pwm_set_irq1_enabled(uint slice_num, bool enabled) {
    check_slice_num_param(slice_num);
    if (enabled) {
        hw_set_bits(&pwm_hw->inte1, 1u << slice_num);
    } else {
        hw_clear_bits(&pwm_hw->inte1, 1u << slice_num);
    }
}
#endif

static inline void pwm_irqn_set_slice_enabled(uint irq_index, uint slice_num, bool enabled) {
    check_slice_num_param(slice_num);
    invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS);
    check_slice_num_param(slice_num);
    if (enabled) {
        hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num);
    } else {
        hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num);
    }
}

static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) {
    valid_params_if(HARDWARE_PWM, slice_mask < 256);
#if PICO_RP2040
    if (enabled) {
        hw_set_bits(&pwm_hw->inte, slice_mask);
    } else {
        hw_clear_bits(&pwm_hw->inte, slice_mask);
    }
#else
    static_assert(PWM_IRQ_WRAP_1 == PWM_IRQ_WRAP_0 + 1, "");
    uint irq_index = PWM_DEFAULT_IRQ_NUM() - PWM_IRQ_WRAP_0;
    if (enabled) {
        hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask);
    } else {
        hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask);
    }
#endif
}

static inline void pwm_set_irq0_mask_enabled(uint32_t slice_mask, bool enabled) {
    // default irq is irq0
    pwm_set_irq_mask_enabled(slice_mask, enabled);
}
 
#if NUM_PWM_IRQS > 1
static inline void pwm_set_irq1_mask_enabled(uint32_t slice_mask, bool enabled) {
    if (enabled) {
        hw_set_bits(&pwm_hw->inte1, slice_mask);
    } else {
        hw_clear_bits(&pwm_hw->inte1, slice_mask);
    }
}
#endif

static inline void pwm_irqn_set_slice_mask_enabled(uint irq_index, uint slice_mask, bool enabled) {
    invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS);
    if (enabled) {
        hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask);
    } else {
        hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask);
    }
}

static inline void pwm_clear_irq(uint slice_num) {
    pwm_hw->intr = 1u << slice_num;
}

static inline uint32_t pwm_get_irq_status_mask(void) {
    return pwm_hw->ints;
}

static inline uint32_t pwm_get_irq0_status_mask(void) {
    return pwm_get_irq_status_mask();
}
 
#if NUM_PWM_IRQS > 1
static inline uint32_t pwm_get_irq1_status_mask(void) {
    return pwm_hw->ints1;
}
#endif

static inline uint32_t pwm_irqn_get_status_mask(uint irq_index) {
    invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS);
    return pwm_hw->irq_ctrl[irq_index].ints;
}

static inline void pwm_force_irq(uint slice_num) {
    pwm_hw->intf = 1u << slice_num;
}

static inline void pwm_force_irq0(uint slice_num) {
    pwm_force_irq(slice_num);
}
 
#if NUM_PWM_IRQS > 1
static inline void pwm_force_irq1(uint slice_num) {
    pwm_hw->intf1 = 1u << slice_num;
}
#endif

static inline void pwm_irqn_force(uint irq_index, uint slice_num) {
    invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS);
    pwm_hw->irq_ctrl[irq_index].intf = 1u << slice_num;
}

static inline uint pwm_get_dreq(uint slice_num) {
    check_slice_num_param(slice_num);
    return PWM_DREQ_NUM(slice_num);
}
 
#ifdef __cplusplus
}
#endif
 
#endif